Socket 7 motherboards, as used by the original Pentium CPU, were clocked at 66MHz (15 nanoseconds per clock tick.) The memory used back then, EDO RAM, typically had timings of 5-2-2-2, meaning that any memory access took five clock ticks to produce the first byte, and then produced three more bytes in the same 32-bit word, one every two ticks.
The first SDRAM (Synchronous Dynamic RAM) had timings of 8-1-1-1 or thereabouts; "Synchronous" referred to the *-1-1-1 timings. A couple of years later, SDRAM was clocked at 133MHz, with timings of 3-1-1-1 (known as CL3) and 2-1-1-1 (CL2). The original DDRAM (Double Data Rate SDRAM) would output a byte on the rising edge and on the falling edge of each clock cycle, so a typical rating of CL2.5 meant timings of 2½-½-½-½.
Dynamic RAM is a design that stores each bit of data on a tiny capacitor that is charged by opening a gate (a single transistor). Charge on capacitors will leak away; the contents of DRAM will be lost unless refreshed (read and rewritten) every few tens of microseconds, which obviously decreases the maximum possible bandwidth. However, the design is cheap. The only viable alternative was virtual memory on a magnetic hard disk, with a latency measured in milliseconds rather than nanoseconds.
Static RAM, which is faster but more expensive to manufacture, is used for the high-speed cache memory integrated on modern CPU dies. A few megabytes of cache memory are perfectly adequate; improving the capacity and price of DRAM are considered a lot more important than improving its speed.
I have difficulty understanding how the timings measured for SDRAM and DDRAM relate to the more complicated ones for DDR-2 and DDR-3; I suspect a degree of obfuscation. Nonetheless, the basic principle of a count of the clock ticks - a division of the clock frequency - still applies.
Now, the quad-core Phenom II is a competent replacement for the Core 2 Quad, avoiding the design problems that forced Intel to disable Hyper-Threading in the latter. The unique selling point of the Core i7 architecture is that the system memory controller has been integrated onto the CPU die, making it easier to clock it much faster than the motherboard chipset, thus ameliorating an obvious performance bottleneck.
This new System Memory Interface is described rather nicely in the datasheet for Intel's LGA-1156 Core i7 (
PDF, 757kB); the feature list on page 7 of the datasheet (
PDF, 866kB) confirms the details are similar for the LGA-1366 version.
The LGA-1366 Core i7 supports single, dual or triple-channel memory access, depending on how many of the three memory channels are occupied. If the channels contain different amounts of memory, it will work in three channels where it can, and use single-channel access for the overspill.
As a consequence of this direct connection, the CPU's I/O subunit is at the same voltage as the DDR-3, so excessive voltage can damage the CPU as well as the DIMMs. The official
DDR-3 standards specify 1.5 volts; Intel have announced (PDF quoted above) a maximum safe value of 1.65V.
Officially, the memory controller operates at 1066MHz (PC3-8500) and at 1333MHz (PC3-10600). The only reason to consider faster DDR-3 is if you want to overclock. As
this guide explains, the Core i7 is particularly elegant to overclock.
BCLK is a system-wide clock signal under motherboard control; every clock frequency in the computer is produced by multiplying BCLK. For example, the Core i7 920 (2666MHz) runs at 20xBCLK, and reduced power settings work by reducing that 20x multiplier. The memory controller lets you choose between 8xBCLK and 10xBCLK. To overclock the system, simply instruct the motherboard BIOS to increase BCLK.
For best performance, I recommend
OCZ RAM. They select their best-performing RAM chips, attach a heatsink and boost the voltage, producing DIMMs that perform (reliably under a dedicated hardware tester, which is much more rigorous than Memtest86+) with much faster timings than are standard.
Their web pages load more quickly if you disable Flash.
All memory DIMMs contain a SPD chip - a ROM chip programmed with the optimal timings for that DIMM, to configure the BIOS automatically. The "Intel Extreme" and "NVidia SLI-ready" DIMMs have Intel's and NVidia's extensions to the SPD standard, that store several different overclocking profiles on the one chip; but I don't recommend them, because the timings they quote are the same as for OCZ's "Gold" Series. The timings given for their Platinum Series are noticeably better.
Their Blade, Flex XLC, Reaper and Platinum Series are the best ones; the only difference between them is the type of heatsink. The ones labelled "Low Voltage" were tested at 1.65V; the others were tested at 1.70V, above Intel's recommended safe maximum.
The bargain price of AMD's Phenom II caused a large upswing in sales of new computers over Christmas, which has led to a shortage of DDR-3. The price per gigabyte is about twice what I paid six months ago. Even though 12GB kits are just beginning to become available, I'd avoid them at the moment.
I've been told that 4.0GHz air-cooled isn't too difficult for a Core i7 (but check for yourself - don't take my word for it); this would mean setting BCLK to 200MHz, and a choice between 1600MHz (PC3-12800) and 2000MHz (PC3-16000) DDR-3. The best timings for OCZ DDR-3 are 6-6-6-24 for PC3-12800, and 9-9-9-30 for PC3-16000. The DDR-3 chips themselves are identical in both cases, but the PC3-16000 version's SPD chip has been programmed with much looser timings; otherwise it couldn't reach 2000MHz at all. You'd gain no DDR-3 speed advantage either way.
Then if you decide not to run the CPU at a 50% overclock, the SPD presets would be awful. You'd have to fiddle around with the BIOS, and change the timings back from 9-9-9-30 to 6-6-6-24 by hand.